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MC44608 Few External Components Reliable and Flexible SMPS Controller
The MC44608 is a high performance voltage mode controller designed for off-line converters. This high voltage circuit that integrates the start-up current source and the oscillator capacitor, requires few external components while offering a high flexibility and reliability. The device also features a very high efficiency stand-by management consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand-by power consumption to approximately 1.0 W while delivering 300 mW in a 150 W SMPS. * Integrated Start-Up Current Source * Lossless Off-Line Start-Up * Direct Off-Line Operation * Fast Start-Up
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8 1 PDIP-8 P SUFFIX CASE 626
Isense Control Input GND
2 3 4
44608Pxxx AWL YYWW
* * * * * * * * * * *
PIN CONNECTIONS AND MARKING DIAGRAM
Flexibility Duty Cycle Control Undervoltage Lockout with Hysteresis On Chip Oscillator Switching Frequency 40, 75, or 100 kHz Secondary Control with Few External Components Maximum Duty Cycle Limitation Cycle by Cycle Current Limitation Demagnetization (Zero Current Detection) Protection "Over VCC Protection" Against Open Loop Programmable Low Inertia Over Voltage Protection Against Open Loop Internal Thermal Protection
Demag
1
8 7 6 5 (Top View)
Vi
Protections
(Top View)
VCC Driver
AWL = Manufacturing Code YYWW = Date Code
ORDERING INFORMATION
Device MC44608P40 MC44608P75 MC44608P100 Switching Frequency Package Shipping 40 kHz 75 kHz 100 kHz Plastic DIP-8 Plastic DIP-8 Plastic DIP-8 50/Rail 50/Rail 50/Rail
SMPS Controller
* Pulsed Mode Techniques for a Very High Efficiency * *
Low Power Mode Lossless Startup Low dV/dT for Low EMI Radiations
(c) Semiconductor Components Industries, LLC, 2001
1
February, 2001 - Rev. 4
Publication Order Number: MC44608/D
MC44608
Demag 1
DMG + 50 mV /20 mV UVLO2 >24 mA >120 m A Latched off Phase Start-up Phase Latched off Phase Start-up Phase OSC Enable Stand-by Management OC NOC Output + CS 1V 4 kHz Filter OSC & 2 mS & Switching Phase OVP UVLO1 UVLO2 OUT Disable DMG & & Thermal S Shutdown PWM Latch RQ Buffer V CC Management 9 mA
Vi 8
Start-up Source
Demag Logic Output Start-up Phase 200 m A Switching Phase 0 & Stand-by
6 V CC
1 S1
Clock
PWM
5 Driver 4 GND
+ -
Leading Edge Blanking
VPWM
2 Isense
Latched off Phase & Stand-by S2 S3 Regulation Block Switching Phase
3 Control Input
Figure 1. Representative Block Diagram
MAXIMUM RATINGS
Rating Total Power Supply Current Output Supply Voltage with Respect to Ground All Inputs except Vi Line Voltage Absolute Rating Recommended Line Voltage Operating Condition Power Dissipation and Thermal Characteristics Maximum Power Dissipation at TA = 85C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature Symbol ICC VCC Vinputs Vi Vi PD RJA TJ TA Value 30 16 -1.0 to +16 500 400 600 100 150 -25 to +85 Unit mA V V V V mW C/W C C
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ELECTRICAL CHARACTERISTICS
Characteristic OUTPUT SECTION Output Resistor Sink Resistance Source Resistance Output Voltage Rise Time (from 3.0 V up to 9.0 V) (Note 1.) Output Voltage Falling Edge Slew-Rate (from 9.0 V down to 3.0 V) (Note 1.) CONTROL INPUT SECTION Duty Cycle @ Ipin3 = 2.5 mA Duty Cycle @ Ipin3 = 1.0 mA Control Input Clamp Voltage (Switching Phase) @ Ipin3 = -1.0 mA Latched Phase Control Input Voltage (Stand-by) @ Ipin3 = +500 mA Latched Phase Control Input Voltage (Stand-by) @ Ipin3 = +1.0 mA CURRENT SENSE SECTION Maximum Current Sense Input Threshold Input Bias Current Stand-By Current Sense Input Current Start-up Phase Current Sense Input Current Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3.0 V) Leading Edge Blanking Duration Leading Edge Blanking Duration Leading Edge Blanking Duration Leading Edge Blanking + Propagation Delay Leading Edge Blanking + Propagation Delay Leading Edge Blanking + Propagation Delay OSCILLATOR SECTION Normal Operation Frequency MC44608P40 Normal Operation Frequency MC44608P75 Normal Operation Frequency MC44608P100 Maximum Duty Cycle @ f = fosc OVERVOLTAGE SECTION Quick OVP Input Filtering (Rdemag = 100 kW) Propagation Delay (Idemag > Iovp to output low) Quick OVP Current Threshold Protection Threshold Level on VCC Minimum Gap Between VCC-OVP and Vstup-th Tfilt TPHL(In/Out) IOVP VCC-OVP VCC-OVP - Vstup - - 105 14.8 1.0 250 2.0 120 15.3 - - - 140 15.8 - ns s A V V fosc fosc fosc dmax 36 68 90 78 40 75 100 82 44 82 110 86 kHz kHz kHz % MC44608P40 MC44608P75 MC44608P100 MC44608P40 MC44608P75 MC44608P100 VCS-th IB-cs ICS-stby ICS-stup TPLH(In/Out) TLEB TLEB TLEB TDLY TDLY TDLY 0.95 -1.8 180 180 - - - - 500 370 300 1.0 - 200 200 220 480 250 200 680 470 420 1.05 1.8 220 220 - - - - 900 570 500 V mA mA mA ns ns ns ns ns ns ns VLP-stby VLP-stby d2mA d1mA - 36 4.75 3.4 2.4 - 43 5.0 3.9 3.0 2.0 48 5.25 4.3 3.7 % % V V V W ROL ROH tr tf 5.0 - - - 8.5 15 50 50 15 - - - ns ns Symbol Min Typ Max Unit
1. This parameter is measured using 1.0 nF connected between the output and the ground.
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ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25C, for min/max values TA = -25C to +85C unless otherwise
noted) (Note 2.) Characteristic DEMAGNETIZATION DETECTION SECTION (Note 3.) Demag Comparator Threshold (Vpin1 increasing) Demag Comparator Hysteresis (Note 4.) Propagation Delay (Input to Output, Low to High) Input Bias Current (Vdemag = 50 mV) Negative Clamp Level (Idemag = -1.0 mA) Positive Clamp Level @ Idemag = 125 mA Positive Clamp Level @ Idemag = 25 mA OVERTEMPERATURE SECTION Trip Level Over Temperature Hysteresis STAND-BY MAXIMUM CURRENT REDUCTION SECTION Normal Mode Recovery Demag Pin Current Threshold K FACTORS SECTION FOR PULSED MODE OPERATION ICCS / Istup ICCS / Istup ICCS / Istup ICCL / Istup (Vstup - UVLO2) / (Vstup - UVLO1) (UVLO1 - UVLO2) / (Vstup - UVLO1) ICS / Vcsth Demag ratio Iovp / Idem NM (V3 1.0 mA - V3 0.5 mA) / (1.0 mA - 0.5 mA) Vcontrol Latch-off SUPPLY SECTION Minimum Start-up Voltage VCC Start-up Voltage Output Disabling VCC Voltage After Turn On Hysteresis (Vstup-th - Vuvlo1) VCC Undervoltage Lockout Voltage Hysteresis (Vuvlo1 - Vuvlo2) Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and (VCC = 9.0 V) Switching Phase Supply Current (no load) MC44608P40 MC44608P75 MC44608P100 Vilow Vstup-th Vuvlo1 Hstup-uvlo1 Vuvlo2 Huvlo1-uvlo2 -(ICC) ICCS - 12.5 9.5 - 6.2 - 7.0 2.0 2.4 2.6 0.3 - - 13.1 10 3.1 6.6 3.4 9.5 2.6 3.2 3.4 0.5 10 50 13.8 10.5 - 7.0 - 12.8 3.6 4.0 4.5 0.68 - V V V V V V mA mA MC44608P40 MC44608P75 MC44608P100 10 x K1 10 x K1 10 x K1 103 102 106 x K2 2.4 2.8 3.1 46 1.8 90 175 3.0 - - 2.9 3.3 7.0 52 2.2 120 198 4.7 1800 4.8 3.8 4.2 4.5 63 2.6 150 225 5.5 - - - - - - - - - - W V Idem-NM 20 25 30 mA Thigh Thyst - - 160 30 - - C C Vdmg-th Hdmg tPHL(In/Out) Idem-lb Vcl-neg-dem Vcl-pos-
dem-H
Symbol
Min
Typ
Max
Unit
30 - - -0.6 -0.9 2.05 1.4
50 30 300 - -0.7 2.3 1.7
69 - - - -0.4 2.8 1.9
mV mV ns mA V V V
Vcl-pos-
dem-L
x Ksstup x Ycstby R3 V3
102 x Ksl Dmgr
Latched Off Phase Supply Current Hiccup Mode Duty Cycle (no load)
ICC-latch dHiccup
mA %
2. Adjust VCC above the start-up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. This function can be inhibited by connecting pin 1 to GND. 4. Guaranteed by design (non tested).
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PIN FUNCTION DESCRIPTION
Pin 1 Name Demag Description The Demag pin offers 3 different functions: Zero voltage crossing detection (50 mV), 24 A current detection and 120 A current detection. The 24 A level is used to detect the secondary reconfiguration status and the 120 A level to detect an Over Voltage status called Quick OVP. The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the power MOSFET. When Isense reaches 1.0 V, the Driver output (pin 5) is disabled. This is known as the Over Current Protection function. A 200 A current source is flowing out of the pin 3 during the start-up phase and during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor and the pin 2, thus a programmable peak current detection can be performed during the SMPS stand-by mode. A feedback current from the secondary side of the SMPS via the opto-coupler is injected into this pin. A resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during the Stand-by mode. This pin is the ground of the primary side of the SMPS. The current and slew rate capability of this pin are suited to drive Power MOSFETs. This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher than 15 V and the operating range is between 6.6 V and 13 V. An intermediate voltage level of 10 V creates a disabling condition called Latched Off phase. This pin is to provide isolation between the Vi pin 8 and the VCC pin 6. Vi This pin can be directly connected to a 500 V voltage source for start-up function of the IC. During the Start-up phase a 9.0 mA current source is internally delivered to the VCC pin 6 allowing a rapid charge of the VCC capacitor. As soon as the IC starts-up, this current source is disabled.
2
Isense
3
Control Input
4 5 6
Ground Driver VCC
7 8
OPERATING DESCRIPTION
Regulation
V CC Control Input V LP-stby 1 S3 0 & Stand-by Latched off Phase
3
1 S2 0 V dd 20 W 5V Switching Phase PWM Regulation Comparator Output 4 kHz Filter
1.6 V
The switch S3 is closed in Stand-by mode during the Latched Off Phase while the switch S2 remains open. (See section PULSED MODE DUTY CYCLE CONTROL). The resistor Rdpulsed (Rduty cycle burst) has no effect on the regulation process. This resistor is used to determine the burst duty cycle described in the chapter "Pulsed Duty Cycle Control" on page 8.
PWM Latch
Figure 2. Regulator
The MC44608 works in voltage mode. The on-time is controlled by the PWM comparator that compares the oscillator sawtooth with the regulation block output (refer to the block diagram on page 2). The PWM latch is initialized by the oscillator and is reset by the PWM comparator or by the current sense comparator in case of an over current. This configuration ensures that only a single pulse appears at the circuit output during an oscillator cycle.
Current Sense
The pin 3 senses the feedback current provided by the opto coupler. During the switching phase the switch S2 is closed and the shunt regulator is accessible by the pin 3. The shunt regulator voltage is typically 5.0 V. The dynamic resistance of the shunt regulator represented by the zener diode is 20 W. The gain of the Control input is given on Figure 11 which shows the duty cycle as a function of the current injected into the pin 3. A 4.0 kHz filter network is inserted between the shunt regulator and the PWM comparator to cancel the high frequency residual noise.
The inductor current is converted to a positive voltage by inserting a ground reference sense resistor RSense in series with the power switch. The maximum current sense threshold is fixed at 1.0 V. The peak current is given by the following equation:
Ipk max + 1 (A) R sense(W)
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In stand-by mode, this current can be lowered as due to the activation of a 200 A current source:
1 * (R cs(kW) 0, 2) Ipk + (A) max *stby R sense(W)
Switching Phase 200 m A 1 0 & STAND-BY START-UP > 24 m A >120 m A Oscillator Buffer Output RQ DMG S + Idemag & 50/20 mV Idemag
Demag
1
DMG
Current Mirror Overcurrent Comparator + 1V OC
Isense
Rsense Rcs
L.E.B.
Figure 4. Demagnetization Block
2
This function can be inhibited by grounding it but in this case, the quick and programmable OVP is also disabled.
Oscillator
Figure 3. Current Sense
The current sense input consists of a filter (6.0 kW, 4.0 pF) and of a leading edge blanking. Thanks to that, this pin is not sensitive to the power switch turn on noise and spikes and practically in most applications, no filtering network is required to sense the current. Finally, this pin is used: - as a protection against over currents (Isense > I) - as a reduction of the peak current during a Pulsed Mode switching phase. The overcurrent propagation delay is reduced by producing a sharp output turn off (high slew rate). This results in an abrupt output turn off in the event of an over current and in the majority of the pulsed mode switching sequence.
Demagnetization Section
The MC44608 contains a fixed frequency oscillator. It is built around a fixed value capacitor CT successively charged and discharged by two distinct current sources ICH and IDCH. The window comparator senses the CT voltage value and activates the sources when the voltage is reaching the 2.4 V/4.0 V levels.
ICH DMG from Demag logic block & SCH 4V 2.4 V SDCH IDCH CT Window + comp OSC Clock
The MC44608 demagnetization detection consists of a comparator designed to compare the VCC winding voltage to a reference that is typically equal to 50 mV. This reference is chosen low to increase effectiveness of the demagnetization detection even during start-up. A latch is incorporated to turn the demagnetization block output into a low level as soon as a voltage less than 50 mV is detected, and to keep it in this state until a new pulse is generated on the output. This avoids any ringing on the input signal which may alter the demagnetization detection. For a higher safety, the demagnetization block output is also directly connected to the output, which is disabled during the demagnetization phase. The demagnetization pin is also used for the quick, programmable OVP. In fact, the demagnetization input current is sensed so that the circuit output is latched off when this current is detected as higher than 120 A.
Figure 5. Oscillator Block
The complete demagnetization status DMG is used to inhibit the recharge of the CT capacitor. Thus in case of incomplete transformer demagnetization the next switching cycle is postpone until the DMG signal appears. The oscillator remains at 2.4 V corresponding to the sawtooth valley voltage. In this way the SMPS is working in the so called SOPS mode (Self Oscillating Power Supply). In that case the effective switching frequency is variable and no longer depends on the oscillator timing but on the external working conditions (Refer to DMG signal in the Figure 6).
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MC44608
OSC 4V Vcont 2.4 V Clock V CC 13 V 10 V 6.5 V
DMG Iprim
Start-up Phase
Latched off Phase
Switching Phase
Figure 7. Hiccup Mode Figure 6.
In case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%.
Mode Transition
The OSC and Clock signals are provided according to the Figure 6. The Clock signals correspond to the CT capacitor discharge. The bottom curve represents the current flowing in the sense resistor Rcs. It starts from zero and stops when the sawtooth value is equal to the control voltage Vcont. In this way the SMPS is regulated with a voltage mode control.
Overvoltage Protection
The MC44608 offers two OVP functions: - a fixed function that detects when VCC is higher than 15.4 V - a programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and compared to the reference current Iovp (120 A). Thus this OVP is quicker as it is not impacted by the VCC inertia and is called QOVP. In both cases, once an OVP condition is detected, the output is latched off until a new circuit START-UP.
Start-up Management
The LW latch Figure 8 is the memory of the working status at the end of every switching sequence. Two different cases must be considered for the logic at the termination of the SWITCHING PHASE: 1. No Over Current was observed 2. An Over Current was observed These 2 cases are corresponding to the signal labelled NOC in case of "No Over Current" and "OC" in case of Over Current. So the effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over current and Q=0 for over current. This sequence is repeated during the Switching phase. Several events can occur: 1. SMPS switch OFF 2. SMPS output overload 3. Transition from Normal to Pulsed Mode 4. Transition from Pulsed Mode to Normal Mode
Latched Off Phase VPWM OUT & NOC OC LEB out 1V + CS S R Q LW Q & & S Q Stand-by & Mode R1 R2
The Vi pin 8 is directly connected to the HV DC rail Vin. This high voltage current source is internally connected to the VCC pin and thus is used to charge the VCC capacitor. The VCC capacitor charge period corresponds to the Start-up phase. When the VCC voltage reaches 13 V, the high voltage 9.0 mA current source is disabled and the device starts working. The device enters into the switching phase. It is to be noticed that the maximum rating of the Vi pin 8 is 500 V. ESD protection circuitry is not currently added to this pin due to size limitations and technology constraints. Protection is limited by the drain-substrate junction in avalanche breakdown. To help increase the application safety against high voltage spike on that pin it is possible to insert a small wattage 1.0 kW series resistor between the Vin rail and pin 8. The Figure 7 shows the VCC voltage evolution in case of no external current source providing current into the VCC pin during the switching phase. This case can be encountered in SMPS when the self supply through an auxiliary winding is not present (strong overload on the SMPS output for example). The Figure 17 also depicts this working configuration.
S1 Switch
Start-up Idemag Switching Start-up Phase > 24 m A Phase Phase
Figure 8. Transition Logic * 1. SMPS SWITCH OFF
When the mains is switched OFF, so long as the bulk electrolithic bulk capacitor provides energy to the SMPS, the controller remains in the switching phase. Then the peak current reaches its maximum peak value, the switching frequency decreases and all the secondary voltages are reduced. The VCC voltage is also reduced. When VCC is equal to 10 V, the SMPS stops working.
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* 2. Overload
In the hiccup mode the 3 distinct phases are described as follows (refer to Figure 7): The SWITCHING PHASE: The SMPS output is low and the regulation block reacts by increasing the ON time (dmax = 80%). The OC is reached at the end of every switching cycle. The LW latch (Figure 8) is reset before the VPWM signal appears. The SMPS output voltage is low. The VCC voltage cannot be maintained at a normal level as the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. Vout nominal / Vout short-circuit). Consequently the VCC voltage is reduced at an operating rate given by the combination VCC capacitor value together with the ICC working consumption (3.2 mA) according to the equation 2. When VCC crosses 10V the WORKING PHASE gets terminated. The LW latch remains in the reset status. The LATCHED-OFF PHASE: The VCC capacitor voltage continues to drop. When it reaches 6.5 V this phase is terminated. Its duration is governed by equation 3. The START-UP PHASE is reinitiated. The high voltage start-up current source (-ICC1 = 9.0 mA) is activated and the MODE latch is reset. The VCC voltage ramps up according to the equation 1. When it reaches 13 V, the IC enters into the SWITCHING PHASE. The NEXT SWITCHING PHASE: The high voltage current source is inhibited, the MODE latch (Q=0) activates the NORMAL mode of operation. Figure 3 shows that no current is injected out pin 2. The over current sense level corresponds to 1.0 V. As long as the overload is present, this sequence repeats. The SWITCHING PHASE duty cycle is in the range of 10%.
* 3. Transition from Normal to Pulsed Mode
according to the equation of the current sense section, page 5. The C.S. clamping level depends on the power to be delivered to the load during the SMPS stand-by mode. Every switching sequence ON/OFF is terminated by an OC as long as the secondary Zener diode voltage has not been reached. When the Zener voltage is reached the ON cycle is terminated by a true PWM action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW latch stores this NOC status. The LATCHED OFF PHASE: The MODE latch is set. The START-UP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1). The SWITCHING PHASE: The Stand-by signal is validated and the 200 A is sourced out of the Current Sense pin 2.
* 4. Transition from Stand-by to Normal
The secondary reconfiguration is removed. The regulation on the low voltage secondary rail can no longer be achieved, thus at the end of the SWITCHING PHASE, no PWM condition can be encountered. The LW latch is reset. At the next WORKING PHASE a NORMAL mode status takes place. In order to become independent of the recovery time constant on the secondary side of the SMPS an additional reset input R2 is provided on the MODE latch. The condition Idemag<24 A corresponds to the activation of the secondary reconfiguration status. The R2 reset insures a direct return into the Normal Mode.
Pulsed Mode Duty Cycle Control
In this sequence the secondary side is reconfigured (refer to the typical application schematic on page 13). The high voltage output value becomes lower than the NORMAL mode regulated value. The TL431 shunt regulator is fully OFF. In the SMPS stand-by mode all the SMPS outputs are lowered except for the low voltage output that supply the wake-up circuit located at the isolated side of the power supply. In that mode the secondary regulation is performed by the zener diode connected in parallel to the TL431. The secondary reconfiguration status can be detected on the SMPS primary side by measuring the voltage level present on the auxiliary winding Laux. (Refer to the Demagnetization Section). In the reconfigured status, the Laux voltage is also reduced. The VCC self-powering is no longer possible thus the SMPS enters in a hiccup mode similar to the one described under the Overload condition. In the SMPS stand-by mode the 3 distinct phases are: The SWITCHING PHASE: Similar to the Overload mode. The current sense clamping level is reduced
During the sleep mode of the SMPS the switch S3 is closed and the control input pin 3 is connected to a 4.6 V voltage source thru a 500 W resistor. The discharge rate of the VCC capacitor is given by ICC-latch (device consumption during the LATCHED OFF phase) in addition to the current drawn out of the pin 3. Connecting a resistor between the Pin 3 and GND (RDPULSED) a programmable current is drawn from the VCC through pin 3. The duration of the LATCHED OFF phase is impacted by the presence of the resistor RDPULSED. The equation 3 shows the relation to the pin 3 current.
Pulsed Mode Phases
Equations 1 through 8 define and predict the effective behavior during the PULSED MODE operation. The equations 6, 7, and 8 contain K, Y, and D factors. These factors are combinations of measured parameters. They appear in the parameter section "Kfactors for pulsed mode operation" page 4. In equations 3 through 8 the pin 3 current is the current defined in the above section "Pulsed Mode Duty Cycle Control".
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EQUATION 1 Start-up Phase Duration: C Vcc (Vstup * UVLO2) I stup
t start-up +
where: Istup is the start-up current flowing through VCC pin CVcc is the VCC capacitor value EQUATION 2 Switching Phase Duration: C Vcc (Vstup * UVLO1) I )I ccS G
t
switch
+
where: IccS is the no load circuit consumption in switching phase IG is the current consumed by the Power Switch EQUATION 3 Latched-off Phase Duration: + C Vcc I (UVLO1 * UVLO2) ccL )I pin3
t
latched*off
where: IccL is the latched off phase consumption Ipin3 is the current drawn from pin3 adding a resistor EQUATION 4 Burst Mode Duty Cycle: + switch )t switch latched*off t
d
BM
t start*up ) t
EQUATION 5 C d + Vcc (V *UVLO1) stup I )I ccS G (V *UVLO1) C (UVLO1*UVLO2) stup ) Vcc I )I I )I ccL pin3 ccS G
BM
C
Vcc
(V * UVLO2) C stup Vcc ) I stup
EQUATION 6 d + 1) I k S Stup 1 )I ccS G I stup ) k SL )I ccS G I )I ccL pin3 I
BM
where: kS/Stup = (Vstup - UVLO2)/(Vstup - UVLO1) kS/L = (UVLO1 - UVLO2)/(Vstup - UVLO1)
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EQUATION 7 d + 1) I )I ccS G I stup k S Stup 1 ) k stup )I ccL pin3 I
BM
SL
I
EQUATION 8 d + 1
BM
1)
k1 )
I I
G
k
stup
S Stup
) (k
SL
1 ) I pin3 k2) I stup
where: k1 = Iccs/Istup k2 = IccL/Istup kS/Stup = (Vstup-UVLO2)/(Vstup-UVLO1) kS/L = (UVLO1-UVLO2)/(Vstup-UVLO1)
PULSED MODE CURRENT SENSE CLAMPING LEVEL
Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired maximum current peak value during the SMPS stand-by mode. EQUATION 9 V * (R cs + cs-th R S I cs)
Ipk
stby
where: Vcs-th is the CS comparator threshold Ics is the CS internal current source RS is the sensing resistor Rcs is the resistor connected between pin 2 and RS EQUATION 10 Ics V cs-th S
1* Ipk stby +V cs-th
R cs R
EQUATION 11 1 * (R cs R Y ) cs-stby S
Ipk
+V stby cs-th
where: Ycs-stby = Ics/Vcs-th Taking into account the circuit propagation delay (dtcs) and the Power Switch reaction time (dtps): EQUATION 12 1 * (R cs R Y ) cs-stby S V ) in (dt cs ) dt ps) Lp
Ipk
stby
+
V cs-th
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60 50 t_rise Frequency Time (nS) 40 t_fall 30 20 10 10 79.0 77.0 75.0 73.0 71.0 69.0 67.0 11 12 13 14 15 65.0 10 11 12 13 14 15 -25 C 25 C
85 C
Pin6 VCC Voltage (V)
VCC Voltage (V)
Figure 9. Output Switching Speed
Figure 10. Frequency Stability
90 80 70 Switching Duty Cycle (%) 60 Vpin3 (V) 50 40 30 20 10 0 0.0 0.5 25 C 85 C -25 C
5.08 5.07 5.06 5.05 5.04 5.03 5.02 5.01 5.00 4.99 1.5 2.0 2.5 4.98 0.5 1 1.5 Current Injected in Pin 3 (mA) 2 2.5 -25 C 85 C 25 C
1.0
Current Injected in Pin3 (mA)
Figure 11. Duty Cycle Control
5.0 4.5 4.0 Vpin3 Voltage (V) 3.5 3.0 2.5 2.0 1.5 -1.6 -1.4 -1.2 -1.0 -.08 -.06 -.04 -.02 0.0 85 C 25 C -25 C Pin6 Current (mA) 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 10
Figure 12. Vpin3 During the Working Period
-25 C
25 C
85 C
11
12
13
14
15
Current Injected in Pin 3 (mA)
Pin6 VCC Voltage (V)
Figure 13. Vpin3 During the Latched Off Period
Figure 14. Device Consumption when Switching
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11.00 -25 C 10.00 9.00 -Icc (mA) 8.00 7.00 85 C 6.00 5.00 Switching Duty Cycle (%) 11.00 10.00 9.00 8.00 7.00 6.00 0 100 200 300 400 500 5.00 0 100 200 300 400 500 25 C 85 C -25 C 12.00
25 C
Vi Pin8 Voltage (Vi)
Vi Pin Voltage (V)
Figure 15. High Voltage Current Source
Figure 16. Overload Burst Mode
Figure 17. Hiccup Mode Waveforms
The data in Figure 16 corresponds to the waveform in Figure 17. The Figure 17 shows VCC, ICC, Isense (pin 2) and Vout (pin 5). Vout (pin 5) in fact shows the envelope of the
output switching pulses. This mode corresponds to an overload condition.
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The Figure 19 represents a complete power supply using the secondary reconfiguration. The specification is as follows: Input source: 85 Vac to 265 Vac 3 Outputs 112 V/0.45 A 16 V/1.5 A 8.0 V/1.0 A Output power 80 W Stand-by mode @ Pout = 300 mW, 1.3 W
R F6 47288900 RFI FILTER
FI WIDE C1 MAINS 100 nF
C20 2N2FY R16 4.7 k W 4 kV D1, D2, D3, D4 1N5404 C5 220 mF 400 V D6 MR856 14
C11 220 pF 500 V D18 MR856 C12 + 47 m F 250 V R1 22 k W 5W C6 47 nF 630 V 6 1 11 D9 MR852 + 7 C9 470 pF 630 V 12 R7 47 k W D12 1N4934 DZ1 MCR22-6 C17 120 pF C13 100 nF
C3 1 nF
112 V/0.45 A 1 2 J3
+ C4 1 nF D5 1N4007 R5 100 k W
3 16 V/1.5 A
1 2 3 8 V/1 A J4
MC44608P75
1
8 7 6 5 VCC R2 10 W
D7 1N4148 + C7 22 m F 16 V 2 10
Isense
C14 1000 m F 35 V
2 3 4
C16 120 pF
R19 18 k W
D13 1N4148 Post Reg.
C8 100 nF R4 3.9 k W
MTP6N60E
D14 MR856 R17 2.2 k W 5W R3 0.27 W
8
D10 MR852 C15 + 1000 m F 16 V
mP
9
R21 47 W OPT1 R10 10 k W ON R8 2.4 k W OFF ON = Normal Mode OFF = Pulsed Mode R9 100 k W R12 1 kW C19 33 nF DZ2 TL431CLP C18 100 nF
R11 4.7 kW
DZ3 10 V
Figure 18. Typical Application
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MC44608
The secondary reconfiguration is activated by the P through the switch. The dV/dt appearing on the high voltage winding (pins 14 of the transformer) at every TMOS switch off, produces a current spike through the series RC network R7, C17. According to the switch position this spike is either absorbed by the ground (switch closed) or flows into the thyristor gate (switch open) thus firing the MCR22-6. The closed position of the switch corresponds to the Pulsed Mode activation. In this secondary side SMPS status the high voltage winding (12-14) is connected through D12 and DZ1 to the 8.0 V low voltage secondary rail. The voltages applied to the secondary windings 12-14, 10-11 and 6-7 (Vaux) are thus divided by ratio N12-14 / N9-8 (number of turns of the winding 12-14 over number of turns of the winding 9-8). In this reconfigured status all the secondary voltages are lowered except the 8.0 V one. The regulation during every pulsed or burst is performed by the zener diode DZ3 which value has to be chosen higher than the normal mode regulation level. This working mode creates a voltage ripple on the 8.0 V rail which generally must be post regulated for the microProcessor supply.
Figure 19. SMPS Pulsed Mode
The Figure 19 shows the SMPS behavior while working in the reconfigured mode. The top curve represents the VCC voltage (pin 6 of the MC44608). The middle curve represents the 8.0 V rail. The regulation is taking place at 11.68 V. On the bottom curve the pin 2 voltage is shown. This voltage represents the current sense signal. The pin 2
voltage is the result of the 200 A current source activated during the start-up phase and also during the working phase which flows through the R4 resistor. The used high resolution mode of the oscilloscope does not allow to show the effective ton current flowing in the sensing resistor R11.
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MC44608
PACKAGE DIMENSIONS
PDIP-8 P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 AC IN DC + IN DC - IN AC IN GROUND OUTPUT AUXILIARY VCC INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8.
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MC44608
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC44608/D

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